Method of simultaneously making a pair of transistors with insulated grids having respectively a fine oxide and a thick oxide, and corresponding integrated circuit comprising such a pair of transistors

ABSTRACT

Forming low-doped NLDD areas  17, 61  of the thin oxide second transistor T 2  includes implanting a first dopant  16  having a first concentration and implanting a second dopant  22  having a second concentration lower than the first concentration. Forming low-doped areas NLDD  61  of the first, thick oxide transistor T 1  includes only said implantation of the second dopant  22.

[0001] The invention relates to microelectronics, in particular tofabricating integrated circuits, and more particularly to fabricating apair of insulated gate transistors simultaneously by a process known inthe art as the “double gate oxide” process.

[0002] The “double gate oxide” process forms simultaneously a firsttransistor having a thick gate oxide layer, for example a layer having athickness of the order of 120 Å, and a second transistor having a thingate oxide layer (i.e. a layer thinner than the gate oxide of the firsttransistor), for example a layer having a thickness of the order of 50Å.

[0003] A thin oxide transistor can be used to implement logic functions.A thick oxide transistor operates at higher voltages than thin oxidetransistors, for example 5 volts, and can be used to implement analogfunctions.

[0004] The skilled person knows that an insulated gate transistor hashigh-doped drain and source regions and low-doped source and drain (LowDoped Drain—LDD) areas extending under the lateral insulative regions(spacers) of the transistor between the high-doped drain and sourceregions and the channel region of the transistor. The thin oxidetransistor requires an abrupt transition between the low-doped sourceand drain area and the channel region to reduce its input/outputresistance and short channel effects.

[0005] However, in the gate double oxide process usually employed, thelow-doped source and drain areas are implanted not only for the thinoxide transistor but also for the thick oxide transistor. For the thickoxide transistor, operating at higher voltages, the sudden transitioncaused by implanting the low-doped source and drain regions causes aproblem of leakage in the turned off state, known as gate-induced drainleakage (GIDL), and a reliability problem (hot carriers).

[0006] The invention aims to provide a solution to this problem.

[0007] The invention aims to improve the “gate double oxide” process sothat a thin oxide transistor and a thick oxide transistor can be madesimultaneously without degrading the performance of the thin oxidetransistor and which improves the performance of the thick oxidetransistor in terms of gate-induced drain linkage (GIDL) andreliability.

[0008] Another object of the invention is to offer this improvement atreduced cost.

[0009] The invention therefore proposes a method of simultaneouslyfabricating a pair of insulated gate transistors, a first transistor ofthe pair having a thicker gate oxide layer than the second transistor ofthe pair. The method includes, for each transistor, forming the gateoxide layer, forming the gate flanked by insulative lateral regions,forming high-doped drain and source regions, and forming low-dopedsource and drain areas extending under the insulative lateral regionsbetween the high-doped drain and source regions and the channel regionof the transistor.

[0010] According to one general feature of the invention, forming sourceand drain areas of the second transistor (i.e. the thin oxidetransistor) includes implanting a first dopant having a firstconcentration and implanting a second dopant having a secondconcentration lower than the first concentration. Also, forming thesource and drain areas of the first transistor (i.e. the thick oxidetransistor) includes only implanting the second dopant.

[0011] In one embodiment of the method, the first dopant is implanted oneither side of the gate of the second transistor (thin oxide transistor)before forming the insulative lateral regions, the active area of thefirst transistor (thick oxide transistor) being protected by a layer ofresin. The second dopant is implanted obliquely, for example at 45°, andsimultaneously from either side of insulative lateral regions associatedwith the gates of the two transistors.

[0012] The first and second transistors can both be N-channeltransistors (NMOS transistors). In this case the first dopant can bearsenic and the second dopant can be phosphorus. Both dopants can bearsenic, however.

[0013] If phosphorus and arsenic are used, for example, the phosphorusNLDD junction of the thick gate oxide transistor is gradual and the NLDDjunction of the thin gate oxide transistor, consisting of phosphorus andarsenic, is still abrupt.

[0014] The first and second transistors can equally well be P-channeltransistors (PMOS transistors). In this case the first dopant and thesecond dopant are advantageously the same and consist of boron.

[0015] The invention also provides an integrated circuit including atleast one pair of insulated gate transistors fabricated by the abovemethod.

[0016] Other advantages and features of the invention will becomeapparent on reading the following description of non-limitingembodiments of the invention and from the accompanying drawings, inwhich FIGS. 1 to 15 show diagrammatically the principal steps of oneembodiment of a process according to the invention for obtaining a pairof transistors according to the invention.

[0017]FIG. 1 shows an initial silicon substrate 10, for example a P-typesubstrate.

[0018] Buried P-type layers 11 have been formed in the substrate 10 by aconventional manner known in the art.

[0019] An N silicon layer has then been grown epitaxially, again in aconventional manner known in the art, and etched locally to formtrenches. Insulative regions 15 are obtained after filling the trencheswith an oxide and polishing mechanically and chemically.

[0020] After protecting the future active area of the thick oxidetransistor with a layer of resin, conventional boron implantation hasformed a P-type caisson 12 and P-type insulative caissons 12.

[0021] After protecting the caisson 12 and the wells 12 with a layer ofresin, further P-type implantation in the active area of the futurethick oxide transistor has produced another caisson 14. Thisimplantation step, which is very familiar to the skilled person, adjuststhe threshold voltage of the future thick oxide transistor to arelatively low value.

[0022] All the steps outlined above are very familiar to the skilledperson and yield a substrate 1.

[0023] A first oxide layer 2, for example a layer of silicon oxide,approximately 100 Å thick is then grown on the top surface of thesubstrate 1.

[0024] After protecting the part 20 of the oxide layer 2 situated abovethe caisson 14 between the two insulative areas 15 with a block 3 ofresin, the layer 2 is then partially etched, as shown in FIG. 2.

[0025] After removing the resin block 3 (FIG. 3), a 50 Å thick secondoxide layer 4 (for example of SiO₂) is grown on the top surface of thesubstrate 1 and on the top surface of the residual portion 20 of theoxide layer 2.

[0026] Growing the oxide layer 4 on the top surface of the siliconproduces a portion 40 which is 50 Å thick. Growing the layer 4 on theresidual portion 20 of silicon dioxide produces a portion 41 of silicondioxide which is only about 20 Å thick.

[0027] The thickness of the gate oxide 2041 above the caisson 14 (FIG.4) is therefore approximately 120 Å. The gate oxide 40 above the caisson13 has a thickness of the order of 50 Å.

[0028] A polysilicon layer 5 is then deposited to form the future gatesof the two transistors in a conventional manner known in the art (FIG.4).

[0029] After applying a resin mask 6 to protect the remainder of thesemiconductor wafer, the gate 5 is pre-implanted with polysilicon 7 sothat the conductivity of the gate material conforms to the type oftransistor to be made. In other words, in this instance, because the aimis to make two N-channel transistors (NMOS transistors), the gatematerial is doped with arsenic, for example, to confer N-typeconductivity on it.

[0030] The geometry of the future gates of the two transistors is thendefined using two resin blocks 8 in a conventional way known in the art(FIG. 6). The polysilicon layer 5 is then etched on either side of theresin blocks 8 until the top surface of the substrate 1 is reached, asshown in FIG. 7, to form the gate 51 of the future transistor T1 with athick oxide layer 401 and the gate 52 of the future transistor T2 with athin oxide layer 402.

[0031] A first dopant 16 with a first concentration is then implanted inthe caisson 13 and in particular on either side of the gate 52 (FIGS. 8and 9). Implanting the first dopant contributes to forming the low-dopedsource and drain areas of the future oxide transistor 20. N-typeimplantation is used in the case of an NMOS transistor (NLDDimplantation). The first dopant 16 is therefore arsenic As, for example.The concentration used is 2×10¹⁴ cm⁻² and the implantation is effectedat an energy of 50 keV.

[0032] Note that the first dopant 16 is implanted before forming theinsulative lateral regions (spacers) of the thin oxide transistor. Also,the active area of the other (thick oxide) transistor is protectedduring implantation by a resin layer 9.

[0033] After removing the resin layer 9, the configuration shown in FIG.9 is obtained; FIG. 9 shows the low-doped implanted areas 17 of thefuture thin oxide transistor; note the absence at this stage oflow-doped areas on either side of the gate 51 of the future thick oxidetransistor.

[0034] A stack of insulative layers 18 formed of tetraethylorthosilicate (TEOS), for example, is then deposited in a conventionalmanner that is known in the art (FIG. 10) to a thickness of the order200 Å, for example, surmounted by a layer of silicon nitride with athickness of 800 Å, for example.

[0035] Etching the stack of layers 18 produces a gate 51 flanked byspacers 181 and a gate 52 flanked by spacers 182.

[0036] After applying a layer of resin 19 to protect the remainder ofthe wafer, conventional implantation 21 is then carried out (FIG. 12) toform the high-doped drain and source regions of the two transistors. Theimplantation 21, intended to impart N⁺ conductivity to the source anddrain regions, is effected with arsenic at a concentration of 4×10¹⁵cm⁻² and at an energy of 60 keV, for example.

[0037] A second dopant 22 is then implanted simultaneously on both sidesof the insulative lateral regions (spacers) 181 and 182 associated withthe gates 51 and 52 of the future transistors.

[0038] Although the second dopant can also be arsenic, it has been notedthat phosphorus is preferable for obtaining the effect that the presentinvention seeks to obtain, as it provides a less abrupt transition thanarsenic. The concentration of the second dopant 22 is of the order of10¹³ cm⁻², for example. Implantation is carried out at an energy of 40keV or less, for example.

[0039] The skilled person will have noted that implantation with thesecond dopant forms the low-doped source and drain areas of the thickoxide transistor T1. Because the implantation is effected on both sidesof the spacers 181 in particular, it is oblique to enable the low-dopedareas to extend under the spacers 181 of the transistor T1.

[0040] Note also that the implantation step 22 could have been carriedout before the implantation step 21.

[0041] When the resin mask 19 is removed, the two transistors T1 and T2shown in FIG. 13 are obtained; the compositions of their low-dopedsource and drain areas and their high-doped source and drain regionswill now be described in more detail, with particular reference to FIGS.14 and 15.

[0042] As shown in FIG. 15, the low-doped source and drain areas of thethick oxide transistor T1 are formed from the area 61 implanted withphosphorus. The area 61 is extended outside the spacer 181 by the N⁺region 21 highly doped with arsenic.

[0043] As for the thin oxide transistor T2 (FIG. 14), the N⁺ drain andsource region 72 highly doped with arsenic is extended under the spacerand under the gate by the low-doped source and drain areas that hereconsist of the arsenic-doped area 17 and the additional implantation ofphosphorus 61.

[0044] The method according to the invention therefore produces a thickgate oxide transistor and a thin gate oxide transistor simultaneously,producing a gradual NLDD junction in the low-doped source and drainareas for the thick oxide transistor and retaining an abrupt NLDDtransition for the thin gate oxide transistor. The additionalimplantation of phosphorus 61 does not alter the abrupt nature of thetransition obtained by the arsenic implanting step 17.

[0045] Although with a conventional double gate oxide process a highleakage current would be observed in the turned off state (zero gatevoltage) and with a drain voltage of 5 V, there is now no leakagecurrent at a drain voltage of 5 V in a thick oxide transistor obtainedby the improved double gate oxide process of the invention. The onset ofa leakage current is pushed back for a drain voltage in the turned offstate of at least 7 V.

[0046] The invention is not limited to the embodiments described, butencompasses all variants thereof.

[0047] It would therefore have been possible, at the stage of theprocess shown in FIG. 8, to free the caisson 14 as well and to implantthe second dopant (for example phosphorus at a low concentration)directly to form the low-doped drain and source areas of the thick oxidetransistor at this stage. At this time, of course, the implantationwould have to be oblique because it would be effected before forming thespacers. However, an embodiment of this kind would have subsequentlynecessitated an additional resin mask to mask the caisson 14 of thethick oxide transistor to perform the arsenic implantation 16 at ahigher dose, completing the formation of the low-doped source and drainareas of the thin oxide transistor.

[0048] The embodiment shown in FIG. 8 therefore has the considerableadvantage of not requiring the use of an additional reticle and anadditional specific masking step to make the two transistorssimultaneously. At the FIG. 8 stage, it is merely necessary to modifythe design of the mask, to extend it at the level of the caisson 14; themask, usually employed in a CMOS fabrication method, and known to theskilled person as an “NLDD mask”, protects the other areas of the waferthat are not to be implanted.

[0049] Finally, although the invention is described in detail here forN-channel transistors, it also applies to the simultaneous production ofP-channel transistors. The skilled person will know how to make thenecessary modifications as to the conductivity types of the variousburied layers and caissons to be used.

[0050] What is more, in the case of producing P-type transistors, thefirst dopant 16 and the second dopant 22 can be boron, for example.

1. A method of simultaneously fabricating a pair of insulated gatetransistors, a first transistor (T1) of the pair having a thicker gateoxide layer than the second transistor (T2) of the pair, said methodincluding, for each transistor, forming the gate oxide layer, formingthe gate flanked by insulative lateral regions, forming high-doped drainand source regions, and forming low-doped source and drain areasextending under the insulative lateral regions between the high-dopeddrain and source regions and the channel region of the transistor,characterized in that forming source and drain areas (17, 61) of thesecond transistor (T2) includes implanting a first dopant (16) having afirst concentration and implanting a second dopant (22) having a secondconcentration lower than the first concentration, and in that formingthe source and drain areas (61) of the first transistor (T1) includesonly implanting the second dopant (22).
 2. A method according to claim1, characterized in that the first dopant (16) is implanted on eitherside of the gate of the second transistor before forming the insulativelateral regions, the active area of the first transistor (T1) beingprotected by a layer of resin (9), and in that the second dopant (22) isimplanted obliquely and simultaneously from either side of insulativelateral regions associated with the gates of the two transistors.
 3. Amethod according to claim 2, characterized in that the first and secondtransistors (T1, T2) are N-channel transistors and in that the firstdopant is arsenic and the second dopant is phosphorus.
 4. A methodaccording to claim 2, characterized in that the first and secondtransistors (T1, T2) are P-channel transistors and in that the firstdopant and the second dopant are boron.
 5. An integrated circuit,characterized in that it includes at least one pair of insulated gatetransistors (T1, T2) fabricated by the method defined in any precedingclaim.